1. Technical Field
The present inventive concept herein relates to memory devices, and more particularly, to a nonvolatile memory device and a method of programming the same.
2. Discussion of the Related Art
Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices have a high read speed and a high write speed. However, the volatile memory devices lose their stored data when their power supplies are interrupted. The nonvolatile memory devices maintain their stored data even when their power supplies are interrupted. Thus, the nonvolatile memory devices are used to remember contents that should be preserved regardless of whether their power is supplied or not.
A flash memory is a type among nonvolatile memories and has a feature of electrically erasing cell data in a block erase operation, and it is thus widely used in computers and memory cards. Each of memory cells of the flash memory device stores 1-bit data or multi-bit data. When 1-bit data is stored in one memory cell, the memory cell has a threshold voltage corresponding to one of two threshold voltage states. When 2-bit data are stored in one memory cell, the memory cell has a threshold voltage corresponding to one of four threshold voltage states. Recently, various technologies to store four or more bit data in one memory cell are actively being studied.
FIG. 1 is a block diagram of a conventional nonvolatile memory device 100. Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110, an address decoder 120, a data input/output circuit 130, a program control logic circuit 140 and a voltage generator 150.
The memory cell array 110 includes memory cells and each memory cell is connected to a bit line and a word line. If one-bit data is stored in one memory cell then the memory cell is called a single level cell (SLC). If two or more bits of data may be stored in one memory cell then the memory cell is called a multi level cell (MLC). The multi level cell (MLC) has to be densely programmed to include threshold voltage states corresponding to the multiple bits being stored within a limited threshold voltage window. Thus, in the case of multi level cells, the reliability of data may be degraded due to interference between cells.
The address decoder 120 selects a word line in response to address information. The address decoder 120 transfers various sorts of word line voltages provided from the voltage generator 150 to the currently selected word line and adjacent wordlines. When a programming operation is performed, the address decoder 120 transfers a program voltage Vpgm of about 15˜20V and a verification voltage Vvfy to the currently-selected word line and transfers a pass voltage Vpass to an unselected word line. When a read operation is performed, the address decoder 120 transfers a selected read voltage Vrd provided from the voltage generator 160 to the currently selected word line and transfers an unselected read voltage Vread of about 5V to the unselected word lines of the same NAND string.
The data input/output circuit 130 is coupled to the memory cell array 110 through the bit lines. The data input/output circuit 130 receives data DATA from the outside and stores the received data in the memory cell array 110. The data input/output circuit 130 reads data DATA stored in the memory cell array 110 and transfers the read data to the outside. The data input/output circuit 130 may include well known constituent elements such as a column select gate, a page buffer, a data buffer, etc. The data input/output circuit 130 may also include well known constituent elements such as a column select gate, a write driver, a sense amplifier, a data buffer, etc.
The program control logic circuit 140 controls the overall operation of the nonvolatile memory device 100 according to a conventional programming method.
The voltage generator 150 generates a DC (direct current) voltage according to a control of the program control logic circuit 140. The voltage generator 150 provides a DC voltage for programming of the nonvolatile memory device 100 in response to a control of the program control logic circuit 140.
FIG. 2 is a circuit diagram of an exemplary implementation of the memory cell array 110 of FIG. 1 in detail. For convenience of description, it is assumed that the memory cell array 110 is implemented with flash memory cells connected to bit lines and word lines the NAND string configuration. Referring to FIG. 2, the memory cell array 110 includes a plurality of string select transistors SST, a plurality of ground select transistors GST and a plurality of flash memory cells MCers, MCw1, MCw2, MCb1, MCb2 and MCd1˜MCd4.
The gate of each string select transistor SST is coupled to the address decoder 120 through a string select line SSL and the drain of each select transistor SST is coupled to the data input/output circuit 130 through corresponding bit line among bit lines BL1˜BLn. The gate of each ground select transistor GST is coupled to the address decoder 120 through the ground select line GSL.
A page of flash memory cells is coupled to each output of the address decoder 120 through a corresponding word line among the word lines WL1˜WLm. In a single level cell (SLC) method, one bit is stored in one memory cell, and the set of flash memory cells connected to one word line constitutes a page. In a multi level cell (MCL) method, a plurality of n bits is stored in one memory cell, and the set of memory cells connected to one word line may constitute a plurality of n pages.
FIG. 3 is a drawing illustrating an example of a conventional threshold voltage distribution of the flash memory cells in FIG. 2. Referring to FIG. 3, the threshold voltage distribution of multi level cell MCL (having 2-bit data stored in each one memory cell) is shown as an illustration.
An erasure state E corresponding to data ‘11’ has the lowest threshold voltage level. Program states of the 2-bit data are arranged by a program state P1 corresponding to data ‘01’, a program state P2 corresponding to data 10 and a program state P3 corresponding to data 00.
The threshold voltage of each memory cell may be affected by the program state of each adjacent memory cell. The threshold voltage of a memory cell may become high or low by a program disturb or by a coupling effect. The threshold voltage of a memory cell in an erasure state may rapidly become higher according to a program state of adjacent memory cell.
If the first memory cell is programmed, the threshold voltage distribution of memory cells forms the distributions illustrated by a solid line. However, by a coupling or program disturb phenomenon according to the programming of adjacent cells, the distributions illustrated by a solid line may shift to the distribution illustrated by a dotted line. The threshold voltage distribution of memory cells in an erasure state E1 may be rapidly widen according to a program state of adjacent memory cells.
Adjacent cells MCw1 and MCw2 in a word line direction, adjacent cells MCb1 and MCb2 in a bit line direction and adjacent cells MCd1˜MCd4 in a diagonal direction are disposed around the memory cell MCers in an erasure state.
In the case that adjacent cells are programmed, the effective threshold voltage of the memory cell (MCers) in an erasure state increases in proportion to a change of threshold voltages of the adjacent cells by a coupling phenomenon. In the case that the threshold voltage of the adjacent cells MCw1 and MCw2 in a word line direction increases by a predetermined level (ΔV), the threshold voltage of the memory cell (MCers) in an erasure state increases by a word line coupling phenomenon. In the case that the threshold voltage of the adjacent cells MCb1 and MCb2 in a bit line direction or the threshold voltage of the adjacent cells MCd1˜MCd4 in a diagonal direction increases by a predetermined level (ΔV), the threshold voltage of the memory cell (MCers) in an erasure state increases by a bit line coupling or a coupling of diagonal direction.
Besides, the threshold voltage of the memory cell MCers in an erasure state may be increased by a program disturb phenomenon. Thus, as illustrated in FIG. 3, a distribution of threshold voltage of the erasure state E1 may be rapidly widen and when performing a read operation, a read failure with respect to memory cell that belongs to may occur.